1. Field of the Invention.
The present invention relates to the field of erasable programmable logic devices and more specifically to current limiting in EPROM arrays
2. Prior Art.
The manufacture and use of electrically programmable read only memories (EPROMs) are a well-known technology in the prior art. Recently, EPROM devices have been combined with programmable logic arrays, or a programmable array logic (PAL), and have provided a new advancement in the area of erasable programmable logic devices (EPLD). A typical EPLD array architecture is disclosed in the U.S. Patent to Hartmann et al., U.S. Pat. No. 4,609,986 Such array architecture utilizes a plurality of EPROM cells which are arranged in a row and column array structure. Although the speed performance of an EPLD device is determined by various properties of the device, a limitation is imposed by the number of EPROM cells which are coupled to a particular bit line.
Typically each device input is divided into an inverting and a non-inverting word line inputs forming the row lines of the array matrix. Therefore, at any given instant of time half of the EPROM cells on a bit line may be conducting. The speed performance is determined by the time required for a plurality of EPROM cells to change from a conducting state to a non-conducting state, or vice versa. The transition phase is dependent upon the number of unprogrammed (erased) EPROM cells selected in a certain column of an array. When multiple cells are conducting, a higher current flow occurs on the bit line which results in a faster discharge and a higher voltage swing between the "on" and "off" states. The increased voltage swing results in a longer period of time required for the bit line to stabilize to its "on" and "off" states, wherein ultimately affecting the speed performance of its device.
It is appreciated that what is needed is an improved circuit to increase the speed performance of an EPLD array by reducing the transistion period between "on" and "off" states on a bit line of the array.